This invention relates to a charge transfer device, and more particularly to a charge detection circuit for detecting charges to be transferred in the form of a signal.
In the prior art solid state image sensor, a charge transfer device such as charge coupled device (CCD) is used to transfer charges obtained by photoelectric conversion process as charge packets. Each of the charge packets is converted to a voltage signal by the charge detection circuit positioned at one end of the CCD, and the voltage signal is used as an output signal of the solid state imaging device.
FIG. 1 is a circuit diagram of the prior art charge detection circuit using a floating diffusion region. This charge detection circuit includes n.sup.+ -type floating diffusion region 13, n.sup.+ -type reset drain region 14, and n-type reset channel 15 all of which are formed, by means of a diffusion process, in p-type semiconductor substrate 11 having an impurity concentration of 10.sup.15 cm.sup.-3. The impurity concentration of n-type reset channel 15 is set at approx. 5.times.10.sup.16 cm.sup.-3.
The n-type transfer channel 12 of the charge detection circuit is formed, by means of a diffusion process, in the surface area of semiconductor substrate 11 such that it is in contact with floating diffusion region 13 The impurity concentration of transfer channel 12 is set at equal to that of reset channel 15. Transfer gate electrodes are insulatively formed over transfer channel 12 and arranged in a direction indicated by arrow A. One of the transfer gate electrodes, which is located at one end of the transfer channel, is used as output gate electrode 16. Charges obtained by means of a photoelectric conversion process are supplied as a charge packet to one end of transfer channel 12, and then transferred in transfer channel 12 under the control of the transfer gate electrodes. When the charge packet is transferred to the other end of transfer channel 12, it is fed from transfer channel 12 into floating diffusion region 13. Floating diffusion region 13 forms a pn junction in cooperation with p-type substrate 11. Therefore, the packet charge can be stored in region 13, due to the presence of the pn junction capacitance and parasitic capacitance associated therewith. The potential of region 13 is determined by the amount of charges stored therein. Source follower amplifier 17 is used to generate voltage signal Vout corresponding to the potential of floating diffusion region 13.
The charge detection circuit additionally includes reset gate electrode 18 which is insulatively formed over reset channel 15. Reset pulse signal RS from pulse generator PG is supplied to reset gate electrode 18 via capacitor 19. When signal RS is at a high potential level, reset channel 15 is set at high potential and to the conductive state in which floating diffusion region 13 and reset drain region 14 are electrically connected to each other. At this time, the charge stored in floating diffusion region 13 is discharged via reset channel 15 into reset drain region 14 which is kept at a potential equal to preset reference potential generated from reference voltage source 20.
In the above-described charge detection circuit, n-type diffusion regions are used to provide transfer channel 12 and reset channel 15 a so-called buried type channel structure. Employing the buried type channel structure enables the voltage applied to reset gate electrode 18--so as to set reset channel 15 into the conductive state, electrically connecting floating diffusion region 13 and reset drain region 14--to be set as low possible.
As is shown in FIG. 1, parasitic capacitor 26 is formed between floating diffusion region 13 and reset gate electrode 18. Therefore, when reset pulse signal RS is changed from the high potential level to the low potential level, to electrically isolate floating diffusion region 13 from reset drain region 14, the potential of floating diffusion region 13 will be shifted due to the rapid variation in the potential level of reset pulse signal RS. Thus, it is necessary to suppress the degree of potential shift to as great an extent as possible. In addition, it is important that reset channel 15 be set in the highly conductive state so that the charge of the charge packet be fully discharged. For this reason, in the prior art, the potential amplitude of reset pulse signal RS is set small, and offset voltage source 25 is provided in addition to reference voltage source 20, to supply an offset voltage which is superposed on pulse signal RS via resistor 21 of high resistance.
FIG. 2 is a waveform diagram of a voltage signal applied to reset gate electrode 18, with RS denoting a reset pulse signal and numeral 27 denoting an offset potential provided by offset voltage source 25. In other words, the signal applied to reset gate electrode 18 is a pulse signal which is biased by the offset potential.
FIG. 3 is a diagram showing the potential distribution of the respective semiconductor regions in the charge detection circuit. In FIG. 3, numeral 61 indicates the potential of reset drain region 14 set to the reference potential, 62 the potential of floating diffusion region 13 transmitted from reset drain region 14 via reset channel 15, 63 the potential of reset channel 15 in the conductive period which is specified by setting reset gate electrode 18 at a high potential, 64 the potential of reset channel 15 in a period in which floating diffusion region 13 is set in the electrically floating condition by setting reset gate electrode 18 at a low potential level, and 65 the potential of transfer channel 12. Assume now that reset pulse signal RS is set low to keep floating diffusion region 13 in the electrically floating condition. When a charge packet is supplied from transfer channel 12 to region 13, the potential of floating diffusion region 13 is changed according to the amount of charges in the charge packet. The potential change is amplified by amplifier 17 and supplied to the exterior.
In the case where the potential amplitude of reset pulse signal RS is reduced to as low a level as possible, it is necessary to take the reduction limit thereof into consideration, which limit is determined by the following relation. That is, the high potential of signal RS must be set to such a potential level that the potential of reset channel 15 may be set higher than the reference potential (potential 61 of reset drain region 14) when signal RS is supplied to reset gate electrode 18. Further, the low potential of signal RS must be set to such a potential level that the potential of floating diffusion region 13 may be set lower than that of reset channel 15 when a charge packet of maximum permissible amount of charges is supplied to floating diffusion region 13. In FIG. 3, .phi.1 indicates the minimum potential amplitude of potential at reset channel 13. In practice, it is necessary for reset pulse signal RS to have a potential amplitude of .phi.1/.gamma.. In this case, .gamma. is a modulation coefficient of the reset channel potential with respect to variation in the reset gate potential and the value of .gamma. is generally set at 0.8 to 0.9.
Unless reference voltage source 20 and offset voltage source 25 are formed to satisfy special specifications, the output voltages thereof will fluctuate in the range of .+-.5%. In a typical charge detection circuit, it is a common practice to use 15 V as an output voltage of reference voltage source 20 and 5 V as an output voltage of offset voltage source 25. Therefore, an output voltage of reference voltage source 20 will fluctuate in the range of .+-.0.75 V and an output voltage of offset voltage source 25 will fluctuate in the range of .+-.0.25 V. In FIG. 3, 66 and 67 indicate a reference potential of +15.75 V, and 68 and 69 indicate a reference voltage of +14.25 V. In the actual circuit design, it is necessary to determine the potential amplitude .phi.2 of the reset channel so that the conduction state can be reliably controlled even when the reference potential is changed as described above. To meet the requirement, the potential amplitude of reset pulse signal RS is determined to .phi.1/.gamma.+ 0.75 V.times.2+0.25 V.times.2 or .phi.1/.gamma.+2 V. In FIG. 3, 70 and 71 indicate the reset channel potential set in the case where the potential amplitude of the reset pulse signal is determined with the fluctuation in the power source voltage taken into consideration. In general, since .phi.1/.gamma. is set at 3 to 4 V, a circuit for generating reset pulse signal RS can be operated on a power source voltage of 5 V used to operate TTL circuits o the like. With the fluctuation of the power source voltage taken into consideration, it is necessary to use a power source voltage exceeding 5 V as .phi.2/.gamma.. Further, reset channel 15 is formed of an n-type diffusion region to have a buried channel structure so that the reset channel potential may vary by +0.5 V with respect to the potential of the reset gate electrode in the case where fluctuation occurs in the manufacturing process, the characteristic of the material and the like. Therefore, it is necessary to further increase .phi.2/.gamma. by 1 V. As a result, it is necessary to use an exclusive power source in order to operate the circuit for generating reset pulse signal RS in the prior art.
As has been described above, two power sources, i.e., a reference voltage source and an offset voltage source, are used to operate the prior art charge detection circuit. In addition, output voltages of the two power sources differ from each other. Therefore, it is necessary to set the amplitude of the reset pulse signal at a high level when the fluctuation in the output voltages is taken into consideration, making it difficult to reduce the size of the prior art charge detection circuit.